The present subject matter relates to a semiconductor design technology, and more particularly, to a clock alignment training operation required in a semiconductor memory device operating at a high speed. In particular, the present subject matter relates to a circuit for preventing a wrong result caused by noise or jitter during the clock alignment training operation from being transferred to an external controller.
In a system including a plurality of semiconductor devices, a semiconductor memory device is used to store data. If a data processing device, e.g., a memory control unit, requires data, the semiconductor memory device outputs data corresponding to addresses coupled from the device requiring the data read-out or stores data provided from the device requiring the data writing in a position corresponding to addresses coupled from the device.
For this purpose, a memory device that is recently being developed and operates at a high speed is designed to input/output two data between a rising edge and a falling edge of a system clock fed from the external, and then to input/output two data between the falling edge and the next rising edge of the system clock. That is, the memory device is designed to input/output 4 data in one period of the system clock.
However, since the system clock is only expressed with two states, i.e., logic high or logic low, there is required a data clock having a frequency that is two times higher than that of the system clock in order to input/output 4 data in one period of the system clock. That is, an exclusive clock is required for such a data input/output.
The semiconductor memory device operating at a high speed uses the system clock as a reference clock when receiving addresses and commands while using the data clock as the reference clock when inputting/outputting data. Therefore, such a semiconductor memory device controls the data clock to have a frequency twice higher than that of the system clock.
By making the data clock to repeat twice for one period of the system clock and the data input/output to occur on each of a rising edge and a falling edge of the data clock, 4 data can be input/output for one period of the system clock.
Unlike a conventional double data rate (DDR) synchronous memory device that uses the system clock as a reference clock to perform a reading or writing operation, the semiconductor memory device operating at a high speed exchanges data using two clocks having different frequencies from each other to perform the reading or writing operation.
However, if a phase of the system clock is not aligned with that of the data clock, a transfer standard of operational commands and addresses is not aligned with a transfer standard of data. In other words, the high-speed operating semiconductor memory device can not normally operate.
Therefore, to make the high-speed operating semiconductor memory device normally operate, an interface training operation between the semiconductor memory device and a data processing device should be performed at the beginning of the operation of the semiconductor memory device.
Herein, the interface training is a training of an interface, which transfers commands, addresses and data to operate at an optimized point before a normal operation is performed between the semiconductor memory device and the data processing device.
The interface training includes address training, clock alignment training (WCK2CK training), read training and write training. Among them, an operation of aligning the data clock and the system clock is performed in the clock alignment training.
FIG. 1 illustrates a block diagram of a conventional circuit for performing the clock alignment training.
According to the clock alignment training, as described above, the high-speed operating semiconductor memory device receives an address signal and a command signal from an external controller on the basis of a system clock HCK and outputs data stored therein to the external controller on the basis of a data clock WCK.
Therefore, if there is a phase difference between the system clock HCK and the data clock WCK, the data stored in the semiconductor memory device arrives at the external controller faster or later as long as a time corresponding to the phase difference.
Thus, the phase difference between the data clock WCK and the system clock HCK, supplied from the external controller, is detected at the beginning of the operation of the high-speed operating semiconductor memory device and the detection result is transferred to the external controller to reduce the phase difference between the system clock HCK and the data clock WCK. This operation is referred to as the clock alignment training.
That is, the conventional circuit for performing the clock alignment training illustrated in FIG. 1 receives a data clock OUT_WCK and a system clock OUT_HCK from the external controller, buffers the data clock OUT_WCK and the system clock OUT_HCK to output a data clock WCK and a system clock HCK, detects the phase difference between the data clock WCK and the system clock HCK, and transfers the detection result to the external controller.
Referring to FIG. 1, the circuit for performing the clock alignment training includes a clock input unit 100, a frequency conversion unit 120, a phase comparison unit 140 and a signal transfer unit 160.
The clock input unit 100 receives the system clock OUT_HCK and the data clock OUT_WCK from the external controller, wherein the system clock OUT_HCK synchronizes input points of an address signal and a command signal, and the data clock OUT_WCK synchronizes an input point of a data signal and has a frequency higher than that of the system clock OUT_HCK. The clock input unit 100 includes a system clock (HCK) input pad 102 for receiving a system clock OUT_HCK from the external controller, a system clock (HCK) input buffer 104 for buffering the system clock OUT_HCK coupled through the HCK input pad 102 and outputting the system clock HCK, a data clock (WCK) input pad 106 for receiving a data clock OUT_WCK from the external controller, wherein the data clock OUT_WCK has a frequency higher than that of the system clock OUT_HCK, and a data clock (WCK) input buffer 108 for buffering the data clock OUT_WCK coupled through the WCK input pad 106 and outputting the data clock WCK.
The frequency conversion unit 120 converts the frequency of the data clock WCK so that the frequency of the data clock WCK becomes identical to that of the system clock HCK.
The phase comparison unit 140 compares a phase of the system clock HCK with a phase of a clock DIV_WCK outputted from the frequency conversion unit 120 and generates a comparison signal COMPARE_SIG corresponding to the comparison result.
The signal transfer unit 160 transfers the comparison signal COMPARE_SIG to the external controller as a training information signal TRAINING_INFO_SIG. The signal transfer unit 160 includes a training information signal (TRAINING_INFO) output buffer 162 for buffering the comparison signal COMPARE_SIG and a training information signal (TRAINING_INFO) output pad 164 for transferring the training information signal TRAINING_INFO_SIG outputted from the TRAINING_INFO output buffer 162 to the external controller.
FIG. 2 is a timing diagram illustrating operational waveforms in case that the circuit illustrated in FIG. 1 performs the clock alignment training in a normal state.
Referring to FIG. 2, although the frequency of the data clock WCK that is inputted to the circuit of performing the clock alignment training according to the prior art from the external controller is higher than that of the system clock HCK, the frequency of the data clock DIV_WCK outputted from the frequency conversion unit 120 becomes identical to that of the system clock HCK since the frequency conversion unit 120 converts the frequency of the data clock WCK.
Before the clock alignment training operation starts, i.e., in a period {circle around (1)}, clock edges of the data clocks WCK and DIV_WCK are not synchronized with that of the system clock HCK. That is, in the period {circle around (1)}, phases of the data clocks WCK and DIV_WCK and the system clock HCK are not synchronized with each other.
After the clock alignment training operation starts, i.e., in periods {circle around (2)}, {circle around (3)}, {circle around (4)}, {circle around (5)} and {circle around (6)}, in order to synchronize the data clocks WCK and DIV_WCK with the system clock HCK, the phases of the data clocks WCK, DIV_WCK are changed while the phase of the system clock HCK is fixed.
Herein, the phases of the data clocks WCK and DIV_WCK are changed corresponding to a logic level of the training information signal COMPARE_SIG (TRAINING_INFO_SIG) that is transmitted to the external controller through the signal transfer unit 160.
In particular, in the periods {circle around (2)}, {circle around (3)}, {circle around (4)}, {circle around (5)} and {circle around (6)}, in which the phases of the data clocks WCK and DIV_WCK are varying since the phases of the data clocks WCK and DIV_WCK and the system clock HCK are not synchronized with each other, the training information signal COMPARE_SIG (TRAINING_INFO_SIG) keeps a logic low level. Meanwhile, in a period {circle around (7)}, in which the phases of the data clocks WCK and DIV_WCK do not need to vary anymore since the data clocks WCK and DIV_WCK are synchronized with the system clock HCK, the training information signal COMPARE_SIG (TRAINING_INFO_SIG) keeps a logic high level.
Consequently, in the circuit for performing the clock alignment training, the phase comparison unit 140 continuously compares the phase of the data clock WCK with that of the system clock HCK inputted from the external controller by performing the clock alignment training operation and the signal transfer unit 160 transmits the comparison result, i.e., the training information signal COMPARE_SIG (TRAINING_INFO_SIG), to the external controller.
FIG. 3 is a timing diagram illustrating operational waveforms in case that the circuit illustrated in FIG. 1 performs the clock alignment training in an abnormal state due to jitter.
Referring to FIG. 3, it is noticed that operational waveforms from a period {circle around (1)}, in which the clock alignment training operation does not start to periods {circle around (2)}, {circle around (3)}, {circle around (4)}, {circle around (5)} and {circle around (6)}, in which the phase of the data clock WCK is synchronized with that of the system clock HCK, are the same as those of the periods in which the phases of the data clock WCK and the system clock HCK are changed from a unsynchronized state to a synchronized state when the clock alignment training is performed in the normal state illustrated in FIG. 2.
Namely, while the phase of the system HCK is fixed, the phases of the data clocks WCK and DIV_WCK vary according to the logic level of the training information signal COMPARE_SIG (TRAINING_INFO_SIG) transmitted to the external controller through the signal transfer unit 160, so that the phase of the data clock WCK is synchronized with that of the system clock HCK.
However, unlike the operational waveforms in case that the clock alignment training operation is performed in the normal state illustrated in FIG. 2, the phases of the data clock WCK and the system clock HCK may be changed by noise or jitter, immediately after the phase of the data clock WCK is synchronized with that of the system clock HCK through the normal clock alignment training operation, i.e. in the period {circle around (6)}. As a result, there may occur a problem that the synchronized phases of the data clock WCK and the system clock HCK become unsynchronized again in periods {circle around (7)} and {circle around (9)}.
In particular, in the periods {circle around (2)}, {circle around (3)}, {circle around (4)}, {circle around (5)} and {circle around (6)}, in which the phases of the data clocks WCK and DIV_WCK vary since the phases of the data clocks WCK and DIV_WCK are unsynchronized with that of the system clock HCK, the training information signal COMPARE_SIG (TRAINING_INFO_SIG) keeps a logic low state continuously. Then, the clock alignment training operation is normally performed and, thus, at the moment when the phase of the data clock WCK is synchronized with that of the system clock HCK, the training information signal COMPARE_SIG (TRAINING_INFO_SIG) transits to a logic high state. However, directly after the training information signal COMPARE_SIG (TRAINING_INFO_SIG) transits to a logic high state, the phase of the system clock HCK is changed by noise or jitter in the period {circle around (7)} and, thus, the phase of the data clock WCK is unsynchronized with that of the system clock HCK again, so that the training information signal COMPARE_SIG (TRAINING_INFO_SIG) transits to the logic low state again.
Likewise, directly after noticing that the training information signal COMPARE_SIG (TRAINING_INFO_SIG) transits to the logic low state according to the phase change of the system clock HCK due to noise or jitter, the synchronization of the phases of the data clock WCK and the system clock HCK succeeds by changing the phase of the data clock WCK. However, directly after that the phase of the data clock WCK is changed, the phase of the data clock WCK is changed by noise or jitter in the period {circle around (9)} and thus the phase of the data clock WCK is unsynchronized with that of the system clock HCK again. As a result, the training information signal COMPARE_SIG (TRAINING_INFO_SIG) transits to the logic low state again.
As described above, although the conventional circuit for performing the clock alignment training operation synchronizes the phase of the data clock WCK with that of the system clock HCK, the phase of the system clock HCK and the phase of the data clock WCK may vary due to noise or jitter and thus the training information signal COMPARE_SIG (TRAINING_INFO_SIG) reporting the result of the clock alignment training operation to the external controller may change its logic level from the logic low state to the logic high state and then from the logic high state to the logic low state continuously.
If the logic level of the training information signal COMPARE_SIG (TRAINING_INFO_SIG) is continuously changed by noise or jitter, there occurs confusion in the external controller that should synchronize the phase of the data clock WCK with that of the system clock HCK and transfer the synchronized clocks to the semiconductor memory device. This confusion forces it to take a long time to perform the clock alignment training operation or there may occur malfunction in the external controller by the wrong clock alignment training.